
22
TS8xCx2X2
4184I–8051–02/08
Interrupt System
The TS80C52X2 has a total of 6 interrupt vectors: two external interrupts (INT0 and
INT1), three timer interrupts (timers 0, 1 and 2) and the serial port interrupt. These inter-
Figure 9. Interrupt Control System
Each of the interrupt sources can be individually enabled or disabled by setting or clear-
ing a bit in the Interrupt Enable register (See
Table 12.). This register also contains a
global disable bit, which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority lev-
els by setting or clearing a bit in the Interrupt Priority register (See
Table 13.) and in the
Interrupt Priority High register (See
Table 14.). shows the bit values and priority levels
associated with each combination.
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another
low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt
source.
If two interrupt requests of different priority levels are received simultaneously, the
request of higher priority level is serviced. If interrupt requests of the same priority level
IE1
0
3
High priority
interrupt
Interrupt
polling
sequence, decreasing from
high to low priority
Low priority
interrupt
Global Disable
Individual Enable
EXF2
TF2
TI
RI
TF0
INT0
INT1
TF1
IPH, IP
IE0
0
3
0
3
0
3
0
3
0
3
Table 11. Priority Level Bit Values
IPH.x
IP.x
Interrupt Level Priority
0
0 (Lowest)
0
1
0
2
1
3 (Highest)